1. Field of the Invention
The invention relates to a thin film transistor, and more particularly, a thin film transistor having polycrystalline silicon as an active layer and a method of manufacturing the same.
2. Discussion of the related Art
Recently, with growing interest regarding information display and an increasing demand for portable media, flat panel display (FPD) devices—with advantages of being thin, light weight and low in power consumption—have been developed and have replaced cathode ray tubes (CRTs). Among theses FPD devices, active matrix liquid crystal display (AM-LCD) devices with their light weight, thin profile and low power consumption have been widely used for notebooks and personal computer monitors because of their superior display quality. An AM-LCD device includes a plurality of pixel regions and thin film transistors, each of which is used as a switching element controlling a voltage applied to a liquid crystal layer of each pixel region to change transmittance of corresponding pixel region.
A liquid crystal display (LCD) device includes a liquid crystal panel displaying images and a driving unit supplying signals to the liquid crystal panel. The liquid crystal panel includes two substrates facing each other and spaced apart from each other with a liquid crystal layer between the two substrates. The two substrates are often referred to as an array substrate and a color filter substrate, respectively. The array substrate includes a plurality of gate lines parallel to each other, a plurality of data lines crossing the plurality of gate lines to define a plurality of pixel regions, a plurality of thin film transistors (TFTs) each connected to each gate line and each data line, and a plurality of pixel electrodes respectively connected to the plurality of TFTs.
A TFT used as a switching element of an LCD device may be classified into an amorphous silicon type and a polycrystalline silicon type according to a phase state of an active layer. Since a TFT using polycrystalline silicon as an active layer has a carrier mobility ten times to a hundred times greater than a TFT using amorphous silicon as an active layer, a driving circuit including the polycrystalline silicon TFTs is more commonly formed for the array substrate. As a result, polycrystalline silicon TFTs may be used as switching elements and driving elements for a next generation display panel having high resolution.
In addition, polycrystalline silicon TFTs may be applied to organic electroluminescent display (OELD) devices, which may alternatively be referred to as organic light emitting diode (OLED) devices, as switching elements. An OELD device includes first and second electrodes and an emitting layer between the first and second electrodes. Electrons and holes are injected into the emitting layer from the first and second electrodes, respectively, and the emitting layer emits light when excitons generated from combination of the electrons and the holes are transited from an excited state to a ground state. Since the OELD device is self emissive and does not require an additional light source, the OELD device has reduced volume and weight.
Hereinafter, a method of manufacturing an array substrate including a polycrystalline silicon thin film transistor according to the related art will be described with reference to accompanying drawings. FIGS. 1A to 1D are cross-sectional views schematically illustrating a method of manufacturing a polycrystalline silicon thin film transistor according to the related art.
In FIG. 1A, a semiconductor area BA, a switching area SA and a pixel region PA are defined on a substrate 10. A semiconductor layer will be formed in the semiconductor area BA, and a thin film transistor will be formed in the switching area SA. The pixel region PA is defined by crossing a gate line and a data line. The semiconductor area BA includes a source area S, a drain area D, and a channel area C. A buffer layer 20 is formed on the substrate 10, where the areas BA, SA, and PA are defined. The buffer layer 20 is formed of an inorganic insulating material group, such as silicon oxide (SiO2) or silicon nitride (SiNX).
Next, an amorphous silicon layer (not shown) is formed on the buffer layer 20 by depositing amorphous silicon (a-Si:H) using a plasma chemical vapor deposition (PCVD) method. The amorphous silicon layer is crystallized and then patterned, thereby forming an active layer 40 in the switching area SA. The buffer layer 20 prevents the amorphous silicon layer from being contaminated by impurities included in the substrate 10 while depositing the amorphous silicon by the PCVD method and crystallizing the amorphous silicon layer. The amorphous silicon layer may be crystallized by an excimer laser annealing (ELA) method, a solid phase crystallization (SPC) method, a sequential lateral solidification (SLS) method, a metal induced crystallization (MIC) method, a metal induced lateral crystallization (MILC) method, or an alternative magnetic lateral crystallization (AMLC) method.
In FIG. 1B, a gate insulating layer 45 is formed on the active layer 40 of FIG. 1A. The gate insulating layer 45 is formed of one selected from an inorganic insulating material group including silicon oxide (SiO2) and silicon nitride (SiNX).
Next, a gate line (not shown) and a gate electrode 25 are formed on the gate insulating layer 45 by forming a gate metallic layer (not shown) and then patterning it. The gate line will be used to supply scan signals. The gate electrode 25 extends from the gate line and overlaps the channel area C. The gate line and the gate electrode 25 are formed of a conductive metallic material group, such as copper (Cu), molybdenum (Mo), aluminum (Al), or aluminum alloy, for example, aluminum neodymium (AlNd). The gate electrode 25 is used as an ion stopper, and a step of highly doping n-type or p-type ions into the active layer 40 of FIG. 1A is performed, thereby forming a semiconductor layer 42 that includes a channel portion 42a, a first doped portion 42b and a second doped portion 42c. The channel portion 42a is disposed under the gate electrode 25 and does not include impurities. The first doped portion 42b and the second doped portion 42c correspond to the source and drain areas S and D, respectively, and include n-type or p-type ions.
Next, a passivation layer 55 is formed substantially on the entire surface of the substrate 10 including the gate line and the gate electrode 25. The passivation layer 55 is formed of one selected from an inorganic insulating material group including silicon oxide (SiO2) and silicon nitride (SiNX) or an organic insulating material group including photo acryl and benzocyclobutene (BCB).
In FIG. 1C, to expose the first and second doped portions 42b and 42c, the passivation layer 55 and the gate insulating layer 45 corresponding to the source and drain areas S and D are sequentially patterned, and thus, a source hole SH and a drain hole DH are formed. The source hole SH exposes the first doped portion 42b in the source area S, and the drain hole DH exposes the second doped portion 42c in the drain area D.
In FIG. 1D, a data line (not shown), a source electrode 32 and a drain electrode 34 are formed on the passivation layer 55 including the source and drain holes SH and DH. The data line perpendicularly crosses the gate line to define the pixel region PA. The source electrode 32 extends from the data line and contacts the first doped portion 42b through the source hole SH. The drain electrode 34 is spaced apart from the source electrode 32 and contacts the second doped portion 42c through the drain hole DH.
An interlayer insulating layer 65 is formed on the substrate 10 including the source and drain electrodes 32 and 34. The interlayer insulating layer 65 includes a drain contact hole DCH exposing the drain electrode 34. The interlayer insulating layer 65 is formed of an inorganic insulating material group, such as silicon oxide (SiO2) or silicon nitride (SiNX), or an organic insulating material group, such as photo acryl or benzocyclobutene (BCB). A pixel electrode 70 is formed in the pixel region PA on the interlayer insulating layer 65 and is connected to the drain electrode 34 through the drain contact hole DCH.
In this manner, the related art polycrystalline silicon thin film transistor can be manufactured. In the above-mentioned process, the source and drain holes SH and DH, which expose the first and second doped portions 42b and 42c corresponding to the source and drain areas S and D, respectively, are formed by a dry-etching method using a plasma dry-etching apparatus. This will be explained hereinafter in more detail with reference to accompanying drawings.
FIG. 2 is a cross-sectional view schematically illustrating a plasma dry-etching apparatus according to the related art. In FIG. 2, the related art plasma dry-etching apparatus 71 includes a chamber 72, a susceptor 80 and an upper electrode 90. The chamber 72 is kept under a vacuum condition. A reactive gas supply unit 84 is formed at one side of a lower part of the chamber 72 and is spaced apart from the susceptor 80. An exhaust unit 88 is formed at another side of the lower part of the chamber 72 and is spaced apart from the reactive gas supply unit 84. The susceptor 80 is disposed in the chamber 72 and functions as a lower electrode. A substrate 10 is disposed on an upper surface of the susceptor 80. The upper electrode 90 is spaced apart from and faces the susceptor 80 in the chamber 72. A ceramic plate 92 is attached at a lower surface of the upper electrode 90.
A space between the susceptor 80 and the upper electrode 90 is defined as a reaction region A under a plasma state. Although not shown in FIG. 2, reactive gases are uniformly injected into the reaction region A by the reactive gas supply unit 84, and residues left after reaction are exhausted outside the chamber 72 through the exhaust unit 88.
Generally, a dry-etching method uses physical reaction due to ion impacts on a surface of the substrate 10, and chemical reaction between reactive materials generated in the plasma or physical and chemical reaction may be used. The chemical dry-etching method is performed by supplying reactive radicals generated in the plasma to a surface of a material to be etched and then forming volatile gases due to the chemical reaction occurring between reactive radicals and atoms at the surface. Since the chemical dry-etching method is an isotropic etching method and the reactor is under vacuum, it is advantageous that volatile gases easily move at the surface.
FIGS. 3A and 3B are cross-sectional views illustrating a step of forming source and drain holes according to the related art. The step of forming the source and drain holes will be explained in greater detail with reference to FIG. 2.
In FIG. 2 and FIG. 3A, a buffer layer 20, a semiconductor layer 42, a gate insulating layer 45, a gate electrode 25 and a passivation layer 55 are sequentially formed on a substrate 10. Source and drain holes SH and DH exposing first and second doped portions 42b and 42c are formed by removing the passivation layer 55 and the gate insulating layer 25. The source and drain holes SH and DH may be formed by a dry-etching method or a wet-etching method. Since there is a limitation of forming fine and minute patterns by the wet-etching method, the source and drain holes SH and DH are mostly formed by the dry-etching method.
Here, photoresist is applied to the passivation layer 55 to form a photoresist layer (not shown), and the photoresist layer is exposed to light through a mask (not shown), which is disposed over the substrate 10 and includes a light-transmitting portion and a light-blocking portion. Then, the photoresist layer is developed and selectively patterned to correspond to source and drain areas S and D, and photoresist patterns 62 are formed. The passivation layer 55 exposed by the photoresist patterns 62 are dry-etched by the dry-etching apparatus of FIG. 2.
The step of forming the source and drain holes SH and DH by sequentially patterning the passivation layer 55 and the gate insulating layer 45 thereunder by the dry-etching method is divided into a first etch step using first reaction gases and a second etch step using second reaction gases. The first reaction gases may include sulfur hexafluoride (SF6) and argon (Ar). The first reaction gases react well with the passivation layer 55, the gate insulating layer 45 and the semiconductor layer 42, that is, silicon nitride (SiNX), silicon oxide (SiO2) and silicon (Si). The second reaction gases may include fluorocarbons (CXFY), argon (Ar) and hydrogen (H2), and more particularly, may include hexafluorobutadiene (C4F6). The second reaction gases react well with the passivation layer 55 and the gate insulating layer 45, that is, silicon nitride (SiNX) and silicon oxide (SiO2), and scarcely react with silicon (Si) of the semiconductor layer 42.
For example, when a thickness t1 of the passivation layer 55 is 4300 Å (Angstroms), and a thickness t2 of the gate insulating layer 45 is 300 Å (Angstroms), the passivation layer 55 corresponding to the source and drain areas S and D is completely patterned by the first reaction gases. Next, in FIG. 3B, the gate insulating layer 45 having the thickness t2 of 300 Å (Angstroms), under the passivation layer 55 is selectively patterned by the second reaction gases, and the semiconductor layer 42 corresponding to the source and drain areas S and D is exposed. At this time, the gate insulating layer 45 may be partially etched by the first reaction gases. After the dry-etching, remaining photoresist patterns 52 may be removed by a stripping process using etchant.
The two patterning process by the first reaction gases and the second reaction gases prevents the semiconductor layer from being damaged. More particularly, if the passivation layer 55 and the gate insulating layer 45 are patterned by only the first reaction gases, the semiconductor layer 42 under the gate insulating layer 45 may be removed together due to properties of the first reaction gases. Since removal of the semiconductor layer 42 by the first reaction gases reduces reliability of the semiconductor layer 42, the passivation layer 55 is patterned by the first reaction gases, and the gate insulating layer 45 is patterned by the second reaction gases that do not react with the semiconductor layer 42, thereby preventing the semiconductor layer 42 from being damaged.
However, the step of forming the source and drain holes SH and DH by the first reaction gases and the second reaction gases increases manufacturing time and costs, and production yield is lowered. In addition, the second reaction gases for selectively exposing the semiconductor layer 42 actively react with polymer materials in the chamber 72 and by-products BP are generated. The by-products BP may stick to an inner wall 74 of the chamber 72. When the gate insulating layer 45 is dry-etched by the second reaction gases, the by-products BP or particles sticking to the inner wall 74 of the chamber 72 may fall onto the substrate 10 due to high frequency voltages and stop the source and drain holes SH and DH. That is, a contact problem wherein the semiconductor layer 42 is not exposed by the by-products or particles may be caused. Accordingly, the inner wall 74 of the chamber 72 must be cleaned and changed periodically. The cleaning and changing are very expensive and reduce operation efficiency. Therefore, the production yield decreases rapidly.
FIG. 4 is a graph illustrating an increase of by-products or particles according to the number of substrates. In FIG. 4, the change of particles is shown as a function of the number of substrates supplied for forming source and drain holes. A first step is a step of initially ashing, a second step is a step of dry-etching using first reaction gases, and a third step is a step of dry-etching using second reaction gases. At this time, in the first and second steps, by-products or particles are slightly changed according as the number of substrates increases, and in the third step, the by-products or particles are rapidly increased. As shown by the experimental data, the inner wall of the chamber is contaminated by the dry etch using the second reaction gases when the source and drain holes are formed.